1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to CMOS transistors and a manufacturing method thereof.
2. Description of the Background Art
In formation of CMOS (Complementary MOS) transistors which use N-channel MOSFETs (referred to as NMOS transistors hereinafter) and P-channel MOSFETs (referred to as PMOS transistors hereinafter) in combination, it is required that the gate electrodes of the NMOS and PMOS transistors suit their respective characteristics.
In MOS transistors having gate lengths up to 0.25 to 0.35 xcexcm, surface-channel type transistors are used as the NMOS transistors and buried-channel type transistors are used as the PMOS transistors, both of which use polysilicon which is doped with impurity, phosphorus (P), as the gate electrodes.
However, the PMOS transistors, adopting the buried-channel structure, are difficult to downsize, since the channel is formed inside the substrate; recent devices therefore adopt the surface-channel structure in both of the NMOS and PMOS transistors, where dual-gate process is becoming common in which N-type impurities are introduced into the gate electrodes of the NMOS transistors and P-type impurities are introduced into the gate electrodes of the PMOS transistors. In contrast to the dual-gate process, a process in which the same type of impurities are introduced into the gate electrodes of both is called a single-gate process.
In the dual-gate process, a layer of non-doped polysilicon is formed as the gate electrodes and impurities are introduced during the gate implantation process and source/drain implantation process.
However, in surface-channel type devices in which the channel is formed right under the gate insulating film, a strong vertical electric field may reduce the carrier mobility. The strong electric field also considerably reduces the reliability under hot-carrier stress and the reliability under bias-temperature stress (NBTI: Negative Bias Temperature Instability).
Accordingly, in recent semiconductor devices having plural kinds of transistors with different operating voltages, e.g. transistors in low-voltage portion which operate at relatively low voltage and transistors in high-voltage portion which operate at relatively high voltage, the performance and reliability of the high-voltage transistors are often sacrificed.
First, referring to FIGS. 30 to 38, a method for manufacturing a semiconductor device having a CMOS transistor 70A and a CMOS transistor 70B is described as an example of the single-gate process. The structure of the CMOS transistor 70A designed for low voltage and that of the CMOS transistor 70B designed for high voltage are shown in FIG. 38 which illustrates the final process step.
First, as shown in FIG. 30, element isolation insulating film 20 is selectively formed in the surface of the silicon substrate 10 to define a low-voltage NMOS region LNR and a low-voltage PMOS region LPR for formation of a low-voltage NMOS transistor and a low-voltage PMOS transistor, and a high-voltage NMOS region HNR and a high-voltage PMOS region HPR for formation of a high-voltage NMOS transistor and a high-voltage PMOS transistor.
Then P well regions PW containing a P-type impurity are formed in the surface of the silicon substrate 10 in the low-voltage NMOS region LNR and the high-voltage NMOS region HNR, and N well regions NW containing an N-type impurity are formed in the surface of the silicon substrate 10 in the low-voltage PMOS region LPR and the high-voltage PMOS region HPR. In the description below, the P well regions PW and the N well regions NW may be simply called a silicon substrate together.
A gate insulating film 41, e.g. an insulating film of silicon oxide, is then formed all over the low-voltage NMOS region LNR and the low-voltage PMOS region LPR on the silicon substrate 10. A gate insulating film 42, e.g. an insulating film of silicon oxide, is formed all over the high-voltage NMOS region HNR and the high-voltage PMOS region HPR on the silicon substrate 10.
The gate insulating film 41 is formed to a thickness of about 0.5 to 3 nm in terms of silicon oxide film thickness, and the gate insulating film 42 is formed to a thickness of about 3 to 10 nm in terms of silicon oxide film thickness.
Then low-concentration impurity layers 30 are formed by introducing a P-type impurity by ion implantation to a relatively low concentration (Pxe2x88x92) into the surface of the silicon substrate 10 in the low-voltage PMOS region LPR and the high-voltage PMOS region HPR. FIG. 30 shows the process in which a P-type impurity is ion-implanted into the high-voltage PMOS region HPR, with the part except the high-voltage PMOS region HPR covered by a resist mask R1 patterned by photolithography. P-type impurity is similarly introduced into the surface of the silicon substrate 10 in the low-voltage PMOS region LPR to form the low-concentration impurity layer 30.
Next, in the process shown in FIG. 31, a non-single-crystal silicon film 50 is applied all over the surface of the silicon substrate 10. This non-single-crystal silicon film 50 is formed of polysilicon or amorphous silicon and contains an N-type impurity, e.g. P (phosphorus).
Next, in the process shown in FIG. 32, the non-single-crystal silicon film 50 is patterned by photolithography to form gate electrodes 51 in the low-voltage NMOS region LNR and the low-voltage PMOS region LPR, and gate electrodes 52 in the high-voltage NMOS region HNR and the high-voltage PMOS region HPR.
Next, in the process shown in FIG. 33, a P-type impurity is introduced by ion implantation to a relatively low concentration (Pxe2x88x92) into the surface of the silicon substrate 10 in the low-voltage PMOS region LPR, so as to form a pair of extension layers 62. FIG. 33 shows the process in which a P-type impurity is ion-implanted into the low-voltage PMOS region LPR by using the gate electrode 51 as an implant mask, with the part other than the low-voltage PMOS region LPR covered by a resist mask R2 patterned by photolithography.
The pair of extension layers 62 are provided in such a manner that they face each other through the low-concentration impurity layer 30 underneath the gate electrode 51. In this case, the region of the silicon substrate 10 located underneath the low-concentration impurity layer 30 serves as the channel region.
The extension layers are impurity layers which form a shallower junction than main source/drain layers formed later; while they should be called source/drain extension layers since they have the same conductivity type as the main source/drain layers and function as source/drain layers, they are called extension layers for convenience. Extension layers are formed also in other regions by similar process.
FIG. 34 shows the structure obtained after the formation of extension layers in the individual regions, where pairs of extension layers 61 and 63 are formed in the surface of the silicon substrate 10 respectively in the low-voltage NMOS region LNR and the high-voltage NMOS region HNR by introducing an N-type impurity to a relatively low concentration (Nxe2x88x92), and pairs of extension layers 62 and 64 are formed in the surface of the silicon substrate 10 respectively in the low-voltage PMOS region LPR and the high-voltage PMOS region HPR by introducing a P-type impurity to a relatively low concentration (Pxe2x88x92).
The pair of extension layers 64 are formed in such a manner that the low-concentration impurity layer 30 is interposed between them.
FIG. 34 shows a process for forming side wall protection film (side wall insulating film) to protect the side walls of the gate electrodes 51 and 52, where an insulating film OX1, e.g. a silicon oxide film, is formed all over the silicon substrate 10.
Subsequently, in the process shown in FIG. 35, the parts of the insulating film OX1 located on top of the gate electrodes 51 and 52 and on the silicon substrate 1 are removed by anisotropic etching, leaving the insulating film OX1 only on the side walls of the gate electrodes 51 and 52, so as to form side wall protecting films 70. In this process, the gate insulating film 41 is also removed in the parts where it is not covered by the gate electrodes 51 and the side wall protecting films 70, and the gate insulating film 42 is also removed in the parts where it is not covered by the gate electrodes 52 and the side wall protecting films 70.
Next, in the process shown in FIG. 36, a resist mask R3 is patterned by photolithography to cover the part except the low-voltage PMOS region LPR, and a P-type impurity is ion-implanted to a relatively high concentration (P+) in the low-voltage PMOS region LPR by using the gate electrode 51 and the side wall protecting films 70 as an implant mask, so as to form a pair of source/drain layers 82 in the surface of the silicon substrate 10. Source/drain layers are similarly formed also in other regions. After the formation of the source/drain layers, damages caused by the ion implantation can be repaired by applying a thermal process.
FIG. 37 shows the structure in which source/drain layers are formed in the individual regions, where pairs of source/drain layers 81 and 83 are formed in the surface of the silicon substrate 10 respectively in the low-voltage NMOS region LNR and the high-voltage NMOS region HNR by introducing an N-type impurity to a relatively high concentration (N+), and pairs of source/drain layers 82 and 84 are formed in the surface of the silicon substrate 10 respectively in the low-voltage PMOS region LPR and the high-voltage PMOS region HPR by introducing a P-type impurity to a relatively high concentration (P+).
Next, in the process shown in FIG. 38, a film of refractory metal, e.g. cobalt (Co), is formed by sputtering to cover the entire surface of the silicon substrate 10 and a high-temperature treatment at 350 to 600xc2x0 C. is applied to form a silicide film in the parts where the refractory metal film is in contact with the exposed surface of the silicon substrate 10 and the exposed surfaces of the gate electrodes 51 and 52. The refractory metal film remaining unsilicidized is removed and a further thermal treatment is applied to form cobalt silicide films (CoSi2) 90; the CMOS transistor 70A designed for low voltage and the CMOS transistor 70B designed for high voltage are thus obtained as shown in FIG. 38.
In FIG. 38, buried-channel type PMOS transistors are formed in the low-voltage PMOS region LPR and the high-voltage PMOS region HPR, and surface-channel type NMOS transistors are formed in the low-voltage NMOS region LNR and the high-voltage NMOS region HNR. Where N-type impurity is introduced in the gate electrodes of the buried-channel type PMOS transistors and it is therefore a single-gate process.
Next, referring to FIGS. 39 to 47, a method for manufacturing a semiconductor device having a CMOS transistor 80A and a CMOS transistor 80B is described as an example of the dual-gate process. The structure of the CMOS transistor 80A designed for low voltage and that of the CMOS transistor 80B designed for high voltage are shown in FIG. 47 which illustrates the final process step. The same components as those shown in the method for manufacturing the low-voltage CMOS transistor 70A and the high-voltage CMOS transistor 70B described referring to FIGS. 30 to 38 are shown at the same reference characters and not described here again.
First, as shown in FIG. 39, a gate insulating film 41, e.g. an insulating film of silicon oxide, is formed all over the low-voltage NMOS region LNR and the low-voltage PMOS region LPR on the silicon substrate 10. A gate insulating film 42, e.g. an insulating film of silicon oxide, is formed all over the high-voltage NMOS region HNR and the high-voltage PMOS region HPR on the silicon substrate 10.
Next, a non-single-crystal silicon film 50A is applied all over the silicon substrate 10. This non-single-crystal silicon film 50A does not contain impurity.
Next, in the process shown in FIG. 40, the non-single-crystal silicon film 50A is patterned by photolithography to form gate electrodes 51A in the low-voltage NMOS region LNR and the low-voltage PMOS region LPR, and gate electrodes 52A in the high-voltage NMOS region HNR and the high-voltage PMOS region HPR.
Next, in the process shown in FIG. 41, a resist mask R2 is patterned by photolithography to cover the part other than the low-voltage PMOS region LPR, and a P-type impurity is introduced by ion implantation to a relatively low concentration (Pxe2x88x92) into the surface of the silicon substrate 10 in the low-voltage PMOS region LPR by using the gate electrode 51A as an implant mask, so as to form a pair of extension layers 62.
FIG. 42 shows a process for, after formation of extension layers in the individual regions, forming side wall protection film (side wall insulating film) to protect the side walls of the gate electrodes 51A and 52A, where an insulating film OX1 of, e.g. silicon oxide, is formed all over the surface of the silicon substrate 10.
Subsequently, in the process shown in FIG. 43, the parts of the insulating film OXI located on top of the gate electrodes 51A and 52A and on the silicon substrate 1 are removed by anisotropic etching, leaving the insulating film OX1 only on the side walls of the gate electrodes 51A and 52A, so as to form side wall protecting films 70. In this process, the gate insulating film 41 is also removed in the parts where it is not covered by the gate electrodes 51A and the side wall protecting films 70, and the gate insulating film 42 is also removed in the parts where it is not covered by the gate electrodes 52A and the side wall protecting films 70.
Next, in the process shown in FIG. 44, a resist mask R3 is patterned by photolithography to cover the part other than the low-voltage PMOS region LPR, and a P-type impurity is ion-implanted to a relatively high concentration (P+) in the low-voltage PMOS region LPR by using the gate electrode 51A and the side wall protecting films 70 as an implant mask, so as to form a pair of source/drain layers 82 in the surface of the silicon substrate 10. In this process step, the P-type impurity is also introduced into the gate electrode 51A, which, with the impurity introduced during formation of the extension layers 62, forms the gate electrode 51A as a gate electrode 512A which contains P-type impurity to the same extent as, or more heavily than, the source/drain layers 82.
Next, in the process shown in FIG. 45, a resist mask R4 is formed to cover the part except the high-voltage PMOS region HPR, and a P-type impurity is ion-implanted to a relatively high concentration (P+) in the high-voltage PMOS region HPR by using the gate electrode 52A and the side wall protecting films 70 as an implant mask, so as to form a pair of source/drain layers 84 in the surface of the silicon substrate 10. In this process step, the P-type impurity is also introduced into the gate electrode 52A, which, with the impurity introduced during formation of the extension layers 64, forms the gate electrode 52A as a gate electrode 522A which contains P-type impurity to the same extent as, or more heavily than, the source/drain layers 84.
Similarly, during formation of source/drain layers 81 and 83 in the low-voltage NMOS region LNR and the high-voltage NMOS region HNR, an N-type impurity is introduced into the gate electrodes 51A and 52A, which, with the impurity introduced during formation of the extension layers 61 and 63, forms gate electrodes 511A and 521A which contain N-type impurity to the same extent as, or more heavily than, the source/drain layers 84.
FIG. 46 shows the structure in which the source/drain layers are formed in the individual regions, where pairs of source/drain layers 81 and 83 are formed in the surface of the silicon substrate 10 respectively in the low-voltage NMOS region LNR and the high-voltage NMOS region HNR by introducing an N-type impurity to a relatively high concentration (N+), and pairs of source/drain regions 82 and 84 are formed in the surface of the silicon substrate 10 respectively in the low-voltage PMOS region LPR and the high-voltage PMOS region HPR by introducing a P-type impurity to a relatively high concentration (P+).
Next, in the process shown in FIG. 47, a film of a refractory metal, e.g. cobalt (Co), is formed by sputtering to cover the entire surface of the silicon substrate 10 and a high-temperature treatment at 350 to 600xc2x0 C. is applied to form silicide film in the parts where the refractory metal film is in contact with the exposed surface of the silicon substrate 10 and the exposed surfaces of the gate electrodes 511A, 512A, 521A and 522A. The refractory metal film remaining unsilicidized is removed and a further thermal treatment is applied to form cobalt silicide films (CoSi2) 90; the low-voltage CMOS transistor 80A and the high-voltage CMOS transistor 80B are thus obtained.
Next, referring to FIGS. 48 to 51, another method for manufacturing the semiconductor device having the CMOS transistor 80A and the CMOS transistor 80B is described. The structure of the CMOS transistor 80A designed for low voltage and that of the CMOS transistor 80B designed for high voltage are the same as those shown in FIG. 47 and therefore not shown in the drawing. The same components as those shown in the method for manufacturing the low-voltage CMOS transistor 70A and the high-voltage CMOS transistor 70B described referring to FIGS. 30 to 38 are shown at the same reference characters and not described here again.
First, as shown in FIG. 48, a non-single-crystal silicon film 50A is applied all over the surface of the gate insulating films 41 and 42. This non-single-crystal silicon film 50A does not contain impurity.
Next, in the process shown in FIG. 49, a resist mask R5 is patterned by photolithography to cover the part except the low-voltage NMOS region LNR and the high-voltage NMOS region HNR, and an N-type impurity is introduced by ion implantation to a relatively high concentration (N+) into the non-single-crystal silicon film 50A, so as to form N-type non-single-crystal silicon films 511 and 521.
Next, in the process shown in FIG. 50, a resist mask R6 is patterned by photolithography to cover the part except the low-voltage PMOS region LPR and the high-voltage PMOS region HPR and a P-type impurity is introduced by ion implantation to a relatively high concentration (P+) into the non-single-crystal silicon film 50A, so as to form P-type non-single-crystal silicon films 512 and 522.
Next, in the process shown in FIG. 51, the non-single-crystal silicon films 511, 512, 521 and 522 are patterned by photolithography to form gate electrodes 511A and 512A in the low-voltage NMOS region LNR and the low-voltage PMOS region LPR, and gate electrodes 521A and 522A in the high-voltage NMOS region HNR and the high-voltage PMOS region HPR. Subsequently, the CMOS transistor 80A for low voltage and the CMOS transistor 80B for high voltage are obtained as shown in FIG. 47 through the process steps described referring to FIGS. 41 to 47.
The manufacturing method described referring to FIGS. 48 to 51 is effective because impurities can be introduced into the gate electrodes independently of the introduction of impurities for formation of the source/drain layers. Besides, when the gate electrodes are formed of a multi-layered film of non-single-crystal silicon and a metal film or a silicide film, the introduction of impurities into the gate electrodes cannot be performed at the same time as the introduction of impurities for formation of the source/drain layers, so the manufacturing method shown in FIGS. 48 and 51 is effective.
As described above, the CMOS transistor 70A and the CMOS transistor 70B have buried-channel type PMOS transistors in the low-voltage PMOS region LPR and the high-voltage PMOS region HPR and surface-channel type NMOS transistors in the low-voltage NMOS region LNR and the high-voltage NMOS region HNR, where it is difficult to achieve size reduction of the buried-channel type MOS transistors.
While the CMOS transistor 80A and the CMOS transistor 80B have no problem with size reduction since the NMOS and PMOS transistors are both surface-channel type, they encounter such problems as the reduction of carrier mobility due to the electric field, reduction of reliability under hot-carrier stress, and reduction of NBTI.
According to a first aspect of the present invention, a semiconductor device comprises: a first NMOS transistor and a first PMOS transistor provided respectively in a first NMOS region and a first PMOS region defined in a surface of a semiconductor substrate; and a second NMOS transistor and a second PMOS transistor provided respectively in a second NMOS region and a second PMOS region defined in the surface of the semiconductor substrate; wherein the second NMOS transistor and the second PMOS transistor have higher operating voltages respectively than the first NMOS transistor and the first PMOS transistor, the second PMOS transistor is a buried-channel type MOS transistor in which a channel is formed in the inside of the semiconductor substrate, and the first NMOS transistor, the first PMOS transistor, and the second NMOS transistor are surface-channel type MOS transistors in which a channel is formed in the surface of the semiconductor substrate.
Preferably, according to a second aspect, in the semiconductor device, the second PMOS transistor comprises a gate insulating film selectively provided on the surface of the semiconductor substrate in the second PMOS region, a gate electrode provided on the gate insulating film, a P-type impurity layer of a relatively low concentration provided in the surface of the semiconductor substrate right under the gate insulating film, and a pair of P-type source/drain layers provided in the surface of the semiconductor substrate outside of sides of the gate electrode and in contact with the impurity layer.
Preferably, according to a third aspect, in the semiconductor device, the pair of P-type source/drain layers comprise a pair of P-type extension layers extending from opposing ends and facing each other.
Preferably, according to a fourth aspect, in the semiconductor device, the gate electrode comprises an N-type impurity at a relatively high concentration.
According to a fifth aspect of the present invention, a semiconductor device manufacturing method comprises the steps of: (a) defining a first NMOS region and a first PMOS region in a surface of a semiconductor substrate respectively for formation of a first NMOS transistor and a first PMOS transistor, and defining a second NMOS region for formation of a second NMOS transistor having a higher operating voltage than the first NMOS transistor and a second PMOS region for formation of a second PMOS transistor having a higher operating voltage than the first PMOS transistor; (b) forming a first gate insulating film in the first NMOS region and the first PMOS region, and forming a second gate insulating film thicker than the first gate insulating film in the second NMOS region and the second PMOS region; (c) forming a P-type impurity layer of a relatively low concentration in the surface of the semiconductor substrate in the second PMOS region; (d) forming a non-single-crystal silicon film containing an N-type impurity at a relatively high concentration on the first and second gate insulating films; (e) introducing a P-type impurity at a relatively high concentration only into the non-single-crystal silicon film in the first PMOS region; and (d) patterning the non-single-crystal silicon film to form gate electrodes respectively in the first NMOS region, the first PMOS region, the second NMOS region, and the second PMOS region.
According to a sixth aspect of the present invention, a semiconductor device manufacturing method comprises the steps of: (a) defining a first NMOS region and a first PMOS region in a surface of a semiconductor substrate respectively for formation of a first NMOS transistor and a first PMOS transistor, and defining a second NMOS region for formation of a second NMOS transistor having a higher operating voltage than the first NMOS transistor and a second PMOS region for formation of a second PMOS transistor having a higher operating voltage than the first PMOS transistor; (b) forming a first gate insulating film in the first NMOS region and the first PMOS region, and forming a second gate insulating film thicker than the first gate insulating film in the second NMOS region and the second PMOS region; (c) forming a P-type impurity layer of a relatively low concentration in the surface of the semiconductor substrate in the second PMOS region; (d) forming a non-single-crystal silicon film containing no impurity on the first and second gate insulating films; (e) introducing an N-type impurity at a relatively high first concentration only into the non-single-crystal silicon film in the first NMOS region, the second NMOS region, and the second PMOS region; and (f) forming gate electrodes by using the non-single-crystal silicon film respectively in the first NMOS region, the first PMOS region, the second NMOS region, and the second PMOS region, and introducing a P-type impurity at a relatively high second concentration into the gate electrode formed in the first PMOS region.
Preferably, according to a seventh aspect, in the semiconductor device manufacturing method, the step (f) comprises a step of, after patterning the non-single-crystal silicon film, and during formation of source/drain layers of the first PMOS transistor, introducing the P-type impurity at the second concentration into the gate electrode formed in the first PMOS region.
Preferably, according to an eighth aspect, in the semiconductor device manufacturing method, the step (f) comprises a step of patterning the non-single-crystal silicon film after introducing the P-type impurity at the second concentration into the non-single-crystal silicon film in the first PMOS region.
Preferably, according to a ninth aspect, in the semiconductor device manufacturing method, the first concentration is equal to or higher than the second concentration.
Preferably, according to a tenth aspect, in the semiconductor device manufacturing method, the step (e) comprises a step of introducing nitrogen into the non-single-crystal silicon film in the first NMOS region, the second NMOS region, and the second PMOS region.
Preferably, according to an eleventh aspect, the semiconductor device manufacturing method further comprises a step (g) of, after patterning the non-single-crystal silicon film, forming by impurity ion implantation pairs of extension layers outside of sides of the gate electrodes, in the surface of the semiconductor substrate, wherein the step (g) comprises a step of simultaneously ion-implanting a P-type impurity by using, as implant masks, the gate electrodes respectively formed in the first and second PMOS regions, so as to form a pair of P-type extension layers in each of the first and second PMOS regions.
Preferably, according to a twelfth aspect, the semiconductor device manufacturing method further comprises a step (g) of, after patterning the non-single-crystal silicon film, forming by impurity ion implantation pairs of extension layers outside of sides of the gate electrodes, in the surface of the semiconductor substrate, wherein the step (g) comprises a step of forming a pair of P-type extension layers only in the surface of the semiconductor substrate in the first PMOS region by using the gate electrode formed in the first PMOS region as an implant mask.
According to the semiconductor device of the first aspect of the present invention, only the second PMOS transistor is a buried-channel type MOS transistor. Electric field applied to the channel is thus reduced and the carrier mobility is enhanced to improve the drain current. Also, while the first NMOS transistor and the first PMOS transistor, which operate at low operating voltage and subjected to low electric field around the channel, are surface-channel type MOS transistors, they are less susceptible to reduction of reliability under hot-carrier stress and reduction of reliability under bias-temperature stress. Furthermore, the buried-channel structure, which is difficult to downsize, is applied only to the second PMOS transistor, which fact facilitates reduction of dimensions of the semiconductor device.
According to the semiconductor device of the second aspect, the presence of the P-type impurity layer provided right under the gate insulating film in the second PMOS transistor causes the channel to form in the inside of the semiconductor substrate, so that the second PMOS transistor can certainly be the buried-channel type.
According to the semiconductor device of the third aspect, the pair of P-type source/drain layers include a pair of P-type extension layers. This suppresses short-channel effect.
According to the semiconductor device of the fourth aspect, the gate electrode of the second PMOS transistor relatively heavily contains N-type impurity. This reduces the electric resistance of the gate electrode.
According to the semiconductor device manufacturing method of the fifth aspect of the present invention, the introduction of impurities for the gate electrodes is performed in the steps (d) and (e) prior to the formation of the gate electrodes; it can thus be performed independently of the introduction of impurities for formation of the source/drain layers, making it easier to control the doses of the impurities introduced. This method is effective when the gate electrodes are composed of a multi-layered film of, e.g. non-single-crystal silicon and a metal film or silicide film, since in this case the introduction of impurities for the gate electrodes cannot be performed at the same time as the introduction of impurities for formation of the source/drain layers.
According to the semiconductor device manufacturing method of the sixth aspect, the introduction of impurities for gate electrodes at least in the first NMOS transistor, the second NMOS transistor and the second PMOS transistor is performed in the step (e) prior to the formation of gate electrodes; it can thus be performed independently of the introduction of impurities for formation of the source/drain layers, making it easier to control the doses of the impurities introduced.
According to the semiconductor device manufacturing method of the seventh aspect, the introduction of impurity into the gate electrode of the first PMOS transistor is performed during formation of the source/drain layers. This simplifies the manufacturing process.
According to the semiconductor device manufacturing method of the eighth aspect, the introduction of impurity for the gate electrode of the first PMOS transistor, too, is performed before formation of the gate electrodes; it can thus be done independently of the introduction of impurities for formation of the source/drain layers so that the doses of the impurities introduced can be controlled easily.
According to the semiconductor device manufacturing method of the ninth aspect, the first concentration, or the concentration of impurity contained in the gates, is equal to or higher than the second concentration, namely the concentration of impurity contained in the source/drain layers. The threshold voltage can thus be controlled.
According to the semiconductor device manufacturing method of the tenth aspect, nitrogen, as well as N-type impurity, is introduced into the non-single-crystal silicon film in the first NMOS region, second NMOS region, and second PMOS region. This prevents diffusion of P-type impurity introduced during formation of the source/drain layers so that the gate electrode can remain N type.
According to the semiconductor device manufacturing method of the eleventh aspect, P-type impurity is ion-implanted simultaneously by using the gate electrodes formed in the first and second PMOS regions as implant masks, so as to form respective pairs of P-type extension layers. This reduces the process for formation of the extension layers.
According to the semiconductor device manufacturing method of the twelfth aspect, a pair of P-type extension layers are formed only in the surface of the semiconductor substrate in the first PMOS region by using the gate electrode formed in the first PMOS region as an implant mask. This reduces the process for formation of the extension layers.
The present invention has been made to solve the problems described earlier, and an object of the present invention is to provide CMOS transistors and a manufacturing method thereof which can satisfy demands for size reduction and demands for reliability.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.